FIG. 8 is a block diagram showing an example configuration of the respective receiving conversion sections 109-1 to 109-n in the conventional receiving-end terminal device 110B shown in FIG. 7. In the receiving conversion section 109 shown in FIG. 8, reference numeral 111 designates a preamplifier (AMP) for amplifying an optical signal modulated by an input electrical signal of 12 Gb/s; and 112 designates an optical/electrical (O/E: Optical/Electrical) interface section which converts the optical signal output from the preamplifier 111 into an electrical signal and outputs an electrical signal of 12 Gb/s. The previously-described identification circuit is disposed within the O/E interface section 112.
Reference numeral 113 designates a demultiplexer (DMUX: De-Multiplexer) which decomposes the electrical signal of 12 Gb/s output from the optical/electrical interface section 112 into 16 electrical signals of 751 Mb/s; and 114 designates a serial/parallel converter (S/P: Serial/Parallel) for converting the 16 electrical signals of 751 Mb/s into 64 electrical signals of 178 Mb/s.
Moreover, reference numeral 115 designates an error correcting decoder (FEC, DEC: Forward-acting Error Correcting code, Decoder) for correcting errors for each signals of 178 Mb/s output from the serial/parallel converter 114.
Reference numeral 116 designates a speed converter (SPD CONV: Speed Converter) for converting a 12 Gb/s-based frame format into an STM-64-based frame format, outputs 64 electrical signals of 155 Mb/s.
Reference numeral 117 designates a parallel/serial converter (abbreviated as P/S in the drawing) for converting 64 electrical signals of 155 Mb/s into 16 electrical signals of 621 Mb/s; 118 designates an electrical/optical converter (abbreviated as E/O in the drawing) for modulating the 16 electrical signals of 621 Mb/s with an optical signal; 119 designates a processor (MP: Maintenance Processor) for managing monitoring and control of the receiving conversion section 109; and 120 designates a control buffer (BUFF: Buffer) which collects the number of error codes from the error correcting decoder 115 in response to a command from the processor 119, thereby providing a response.
FIG. 9 is a block diagram showing an example configuration of the above-described conventional optical/electrical interface 112. The optical/electrical interface section 112 comprises a photodiode (Photodiode: PD) 121, an amplifier 122, an equalizer (EQL) 123, a timing extraction section (TIM) 124, a D-flip flop (D-FF) 125, and a reference voltage holding section 126.
The photodiode 121 receives the optical signal (the optical signal having been subjected to wavelength demultiplexing) output from the AMP 111 shown in FIG. 8 and outputs an electrical signal (a voltage signal) having an amplitude value corresponding to the intensity of the optical signal. The amplifier 122 amplifies the electrical signal output from the photodiode 121.
The equalizer 123 subjects the electrical signal amplified by the amplifier 122 to equalization processing. The timing extraction section 124 extracts, from the electrical signal output from the amplifier 122, a timing component used for extracting a modulated signal component in a subsequent stage, and outputs the extracted timing component as a clock signal.
The D-flip flop 125 compares the signal output from the equalizer 123 as a data signal with the fixed voltage value held by the reference voltage holding section 126, and outputs a signal corresponding to the result of comparison in synchronism with the clock signal output from the timing extraction section 124.
The optical signal received by the photodiode 121 is formed as a result of amplitude modulation of the data signal of 12 Gb/s in any of the transmission conversion sections 101-1 to 101-n of the transmission-end terminal device 110A. The above-described D-flip flop 125 can demodulate the thus-modulated signal and output the thus-demodulated signal as a digital signal.
Consequently, the D-flip flop 125 is arranged to take an identification point determined by the voltage held by the reference voltage holding section 126 and the phase of the clock signal output from the timing extraction section 124, and to output a digital (digitized) signal consisting of a “1” or “0” logic level in synchronism with the clock signal. Thus the D-flip flop 125 is configured as an identification circuit which demodulate the digital signal of 12 Gb/s modulated by a change in intensity with respect to the time axis.
FIGS. 10A and 10B are views showing a relationship between a waveform of the data signal (voltage signal) input to the above-described D-flip flop 125 and the identification point I. In the drawing, the horizontal axis denotes time, and the vertical axis denotes amplitude. As shown in FIGS. 10A and 10B, the identification point I is determined by the fixed voltage value held by the reference voltage holding section 126 and the phase of the clock signal output from the timing extraction section 124.
The maximum amplitude level corresponds to a logic level 1, and the minimum amplitude level corresponds to a logic level 0. Since there is a chance of the logic level of the transmitted information changing during a duration of one bit corresponding to a transmission speed, there exists a point at which the logic level is switched every duration of one bit. An area surrounded by the logic level of 1, the logic level of 0, and a transient state achieved before and after the switching point is called an eye pattern.
In reality, the eye pattern becomes narrow because the logic level of 1, the logic level of 0, and the transient state achieved before and after the switching point change on a per-bit basis. FIG. 10(a) shows the eye pattern acquired in an appropriate condition, and FIG. 10(b) shows the eye pattern acquired when the transmission signal has undergone deterioration or the like.
In the case of the eye pattern such as that shown in FIG. 10(a), the D-flip flop 125 can perform identification processing of a received waveform with high accuracy even when the fixedly-set identification point voltage is used, and hence the code error rate is minimized during identification, so that the transmission quality becomes maximum.
In contrast, as shown in FIG. 10(b), when fluctuations have arisen in the loss of the transmission channel or in the gain of the optical fiber amplifier, the amplitude of the received waveform has become smaller than that which is achieved in a condition shown in FIG. 10(a). When the fixedly-set identification point voltage I is used, difficulty is encountered by the D-flip flop 125 in carrying out identification operation with high accuracy, thereby deteriorating the code error rate and obstructing an improvement in transmission quality.
Put another way, as a result of pursuit of an increase in transmission distance and capacity of the optical communications system, the received signal that has been transmitted and input to the receiver is subjected to fluctuations for reasons of various fluctuation factors from short-term and long-term points of view. As a result, the optimum identification point of the signal identification circuit in the receiver also similarly fluctuates.
In other words, although the identification circuit 125 of the above-described receiving-end terminal device 110B in the wavelength-multiplexed optical transmission system uses the identification point set the voltage to a fixed value, it is desired to change the voltage of the identification point according to a transmission characteristic in order to minimize the code error in the demodulation.
Alternatively, in the wavelength-multiplexed optical transmission system, the gain of the optical fiber amplifier has wavelength dependence. Although there is a technique for lessening the wavelength dependence through use of a variable optical equalizer, equalization residues are accumulated with an increase in the number of stages of the optical fiber amplifiers in the long-distance transmission channel, so that variations in the level of the code, which arise on a per-wavelength basis, are unavoidable. Consequently, in such a case, each receiving converter must be controlled to a different identification point and make the identification processing.
The present invention has been conceived in view of such a drawback and aims at providing an optical signal receiver and a method for controlling an identification point for binarization processing performed thereby, wherein a code error rate is diminished by optimally tracking an identification point at all times in accordance with a received signal, thereby maintaining transmission quality high.